The present invention relates generally to testing the performance of microelectronic circuits, and more specifically to process monitors using ring oscillators to measure the speed performance of each product die on a processed wafer.
Each product die on a processed wafer contains many circuits. A process monitor is a test circuit created on each die to track or measure the performance i.e., the propagation delay, of logic paths within the core of the product die. The performance measurements may be used to identify the position of the processed wafer in the performance distribution and/or to sort a die based on performance. A disadvantage of current tracking methods is that the gate structures or cell types used in the process monitor delay chain are not representative of those used in the die core. Another disadvantage is that metal loading is not incorporated into the process monitor measurements. A further disadvantage is that the measurements are subject to error due to internal and external loading. For example, the process monitor measurements are typically made of the width of pulses generated by the process monitor. The test probe used to sense the pulse and the routing of the process monitor output to the test probe may significantly distort the pulse shape. Reading the pulse width from the distorted pulse shape results in inconsistency and inaccuracy in the pulse width measurements.
The present invention advantageously addresses the needs above as well as other needs by providing a process monitor for measuring net chain delay.
In one embodiment, the present invention may be characterized as a process monitor that includes a test circuit formed on a product die wherein the test circuit has a distribution of cell types that is substantially identical to that of the product die.
In another embodiment, the present invention may be characterized as a method for process monitoring that includes the steps of generating pulses from a test circuit formed on a product die and counting the pulses output by the test circuit during a counting interval to measure a net chain delay of the test circuit wherein the net chain delay of the test circuit is representative of a net chain delay of a plurality of circuits formed on the product die.